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• W2134731385 abstract "This paper describes a fail situation in the mass product testing of the embedded NAND-type mask ROM of a SOC of passing in the high speed test, but fails in the low speed test, and propose a fault model of the situation. We also propose a general solution of testing to cope with this fault model. Finally, we invent DFT architecture to cover the fault model to reduce the testing time." @default.
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• W2134731385 date "2005-01-01" @default.
• W2134731385 modified "2023-09-23" @default.
• W2134731385 title "DFT architecture for a dynamic fault model of the embedded mask ROM of SOC" @default.
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• W2134731385 doi "https://doi.org/10.1109/mtdt.2005.8" @default.
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