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- W2134982303 abstract "This paper analyses the ESD robustness of vertically integrated DMOS transistors. The relation between the snapback current (I/sub sb/) and the device layout, and between the thermal failure current (I/sub tf/) and the buried layer process conditions is established. The physical mechanisms responsible for hot spot hopping between two adjacent vertical bipolars; are highlighted. Optimisation for ESD robustness means giving up on R/sub on/. The optimum process and layout conditions are determined." @default.
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- W2134982303 date "2004-01-01" @default.
- W2134982303 modified "2023-10-16" @default.
- W2134982303 title "Optimization of integrated vertical DMOS transistors for ESD robustness" @default.
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- W2134982303 doi "https://doi.org/10.1109/wct.2004.239936" @default.
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