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• W2135193485 abstract "We propose a floorplan-aware complexity reduction methodology for digital filters. Conventional methodologies for complexity reduction use logic-centric approaches focusing on the total number of adders. Therefore, there is a need to consider interconnects to reduce communication costs while synthesizing reduced-complexity filters. In this paper, we integrate high-level synthesis and floorplan to obtain improvement in both computational complexity and interconnect delay. In our experiments, we could achieve 15% improvement in critical-path delay over conventional methodologies." @default.
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• W2135193485 date "2006-02-01" @default.
• W2135193485 modified "2023-10-18" @default.
• W2135193485 title "Layout-driven architecture synthesis for high-speed digital filters" @default.
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• W2135193485 doi "https://doi.org/10.1109/tvlsi.2005.863741" @default.
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