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• W2135689375 abstract "An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBM's 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA." @default.
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• W2135689375 date "2004-08-13" @default.
• W2135689375 modified "2023-09-28" @default.
• W2135689375 title "Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs" @default.
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• W2135689375 doi "https://doi.org/10.1109/relphy.2004.1315313" @default.
• W2135689375 hasPublicationYear "2004" @default.
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