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- W2135751519 abstract "A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix." @default.
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- W2135751519 date "2009-06-30" @default.
- W2135751519 modified "2023-10-04" @default.
- W2135751519 title "Low-Power Bus Architecture Composition for AMBA AXI" @default.
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- W2135751519 doi "https://doi.org/10.5573/jsts.2009.9.2.075" @default.
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