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- W2136026969 abstract "In this article we propose a novel scheme based on virtually scaling-free COordinate Rotation DIgital Computer (CORDIC) algorithm to design a hardware efficient CORDIC rotator. For predicting rotation directions, less than 1/3 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>rd</sup> of the elementary rotational stages require classical CORDIC iteration. The rest of the iteration directions could be computed in parallel and the corresponding z-datapath could be eliminated. A 16-bit implementation of the processor requires 0.23 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> silicon area and consumes 967.8 μW power when synthesized in 0.18 μm technology." @default.
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- W2136026969 date "2008-05-01" @default.
- W2136026969 modified "2023-10-14" @default.
- W2136026969 title "Reduced Z-datapath Cordic Rotator" @default.
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- W2136026969 doi "https://doi.org/10.1109/iscas.2008.4542182" @default.
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