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- W2137148614 abstract "This paper will describe two 30K-gate chips which have been designed and fabricated to transmit and receive CEFT4 and STM-1 signals at 140 Mbiti sec and 156 Mbitisec data rate operations for SDHiSONET 2.5 Gbitisec transmission systems. A mixed full custom and standard cell design technique has been demonstrated to be very effective in providing short design intervals and attractive costs for high speed, low power systems." @default.
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- W2137148614 date "2005-08-24" @default.
- W2137148614 modified "2023-09-26" @default.
- W2137148614 title "Two 156 Mbit/sec CMOS Chips For Sdh/Sonet 2.5 Gbit/sec European Transmission Systems" @default.
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- W2137148614 doi "https://doi.org/10.1109/cicc.1992.591307" @default.
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