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- W2137180836 abstract "Novel BiNoC router architecture is presented that supports dynamic self-reconfiguration of channel direction and buffer reconfiguration. In conventional BiNoC architecture to accommodate heavy traffic, large buffer is needed. But the proposed router (BiNoC router with reconfigurable buffer) can support heavy traffic without the need of large buffer. In this case power dissipation is less and performance is better than conventional BiNoC router. The designing has been done using the hardware description language VHDL in XILINX ISE tool. Its FPGA implementation is done using Virtex-5 board." @default.
- W2137180836 created "2016-06-24" @default.
- W2137180836 creator A5055405423 @default.
- W2137180836 date "2014-08-25" @default.
- W2137180836 modified "2023-09-27" @default.
- W2137180836 title "Design and Implementation of Buffer Loan Algorithm for BiNoC Router" @default.
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- W2137180836 doi "https://doi.org/10.14445/22315381/ijett-v14p218" @default.
- W2137180836 hasPublicationYear "2014" @default.
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