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• W2137442640 abstract "When test vectors for a full scan logic circuit include unspecified values, conventional 3-valued fault simulation may not compute the exact fault coverage for single stuck-at faults. This paper first addresses the incompleteness of logic/fault simulation based on the conventional 3-valued logic. Then we propose an enhanced method of logic/fault simulation to compute more accurate fault coverage using implicit logic values. The proposed method employs indirect implications. We also propose a new learning criterion to identify indirect implications that are not identified by earlier static learning procedure. Since some indirect implications derived from a fault-free circuit become invalid in the presence of a fault, we use a sufficient condition for an indirect implication to remain valid for the faulty circuit, and give an efficient procedure for more accurate fault simulation. Experimental results demonstrate that the proposed method reduces the number of unknown values at the circuit outputs in logic simulation, and hence it discovers several detected faults that are not declared as detected by the conventional fault simulation." @default.
• W2137442640 created "2016-06-24" @default.
• W2137442640 creator A5040022092 @default.
• W2137442640 creator A5045620756 @default.
• W2137442640 creator A5077101123 @default.
• W2137442640 date "2004-11-08" @default.
• W2137442640 modified "2023-09-24" @default.
• W2137442640 title "Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values" @default.
• W2137442640 cites W1554885925 @default.
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• W2137442640 doi "https://doi.org/10.1109/etsym.2004.1347620" @default.
• W2137442640 hasPublicationYear "2004" @default.
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