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• W2137560215 endingPage "826" @default.
• W2137560215 startingPage "821" @default.
• W2137560215 abstract "With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions. With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions." @default.
• W2137560215 created "2016-06-24" @default.
• W2137560215 creator A5007116603 @default.
• W2137560215 creator A5008798516 @default.
• W2137560215 creator A5018379640 @default.
• W2137560215 creator A5049776906 @default.
• W2137560215 date "2009-04-20" @default.
• W2137560215 modified "2023-09-27" @default.
• W2137560215 title "Process variation aware thread mapping for chip multiprocessors" @default.
• W2137560215 cites W1510263988 @default.
• W2137560215 cites W1517661712 @default.
• W2137560215 cites W1969008267 @default.
• W2137560215 cites W1971851724 @default.
• W2137560215 cites W1991353737 @default.
• W2137560215 cites W2022740893 @default.
• W2137560215 cites W2033443176 @default.
• W2137560215 cites W2037437823 @default.
• W2137560215 cites W2055112469 @default.
• W2137560215 cites W2099320289 @default.
• W2137560215 cites W2102081731 @default.
• W2137560215 cites W2102590609 @default.
• W2137560215 cites W2107069215 @default.
• W2137560215 cites W2109173886 @default.
• W2137560215 cites W2117154099 @default.
• W2137560215 cites W2117648153 @default.
• W2137560215 cites W2146018705 @default.
• W2137560215 cites W2154054117 @default.
• W2137560215 cites W2157210245 @default.
• W2137560215 cites W2162847528 @default.
• W2137560215 cites W2165126103 @default.
• W2137560215 cites W2170509664 @default.
• W2137560215 doi "https://doi.org/10.5555/1874620.1874821" @default.
• W2137560215 hasPublicationYear "2009" @default.
• W2137560215 type Work @default.
• W2137560215 sameAs 2137560215 @default.
• W2137560215 citedByCount "14" @default.
• W2137560215 countsByYear W21375602152012 @default.
• W2137560215 countsByYear W21375602152013 @default.
• W2137560215 countsByYear W21375602152014 @default.
• W2137560215 countsByYear W21375602152015 @default.
• W2137560215 countsByYear W21375602152017 @default.
• W2137560215 countsByYear W21375602152018 @default.
• W2137560215 crossrefType "proceedings-article" @default.
• W2137560215 hasAuthorship W2137560215A5007116603 @default.
• W2137560215 hasAuthorship W2137560215A5008798516 @default.
• W2137560215 hasAuthorship W2137560215A5018379640 @default.
• W2137560215 hasAuthorship W2137560215A5049776906 @default.
• W2137560215 hasConcept C111919701 @default.
• W2137560215 hasConcept C11413529 @default.
• W2137560215 hasConcept C115537543 @default.
• W2137560215 hasConcept C121332964 @default.
• W2137560215 hasConcept C138101251 @default.
• W2137560215 hasConcept C149635348 @default.
• W2137560215 hasConcept C157742956 @default.
• W2137560215 hasConcept C163258240 @default.
• W2137560215 hasConcept C165005293 @default.
• W2137560215 hasConcept C173608175 @default.
• W2137560215 hasConcept C2524010 @default.
• W2137560215 hasConcept C33923547 @default.
• W2137560215 hasConcept C41008148 @default.
• W2137560215 hasConcept C45374587 @default.
• W2137560215 hasConcept C53833338 @default.
• W2137560215 hasConcept C62520636 @default.
• W2137560215 hasConcept C76155785 @default.
• W2137560215 hasConcept C78766204 @default.
• W2137560215 hasConcept C82876162 @default.
• W2137560215 hasConcept C93389723 @default.
• W2137560215 hasConcept C98045186 @default.
• W2137560215 hasConcept C99844830 @default.
• W2137560215 hasConceptScore W2137560215C111919701 @default.
• W2137560215 hasConceptScore W2137560215C11413529 @default.
• W2137560215 hasConceptScore W2137560215C115537543 @default.
• W2137560215 hasConceptScore W2137560215C121332964 @default.
• W2137560215 hasConceptScore W2137560215C138101251 @default.
• W2137560215 hasConceptScore W2137560215C149635348 @default.
• W2137560215 hasConceptScore W2137560215C157742956 @default.
• W2137560215 hasConceptScore W2137560215C163258240 @default.
• W2137560215 hasConceptScore W2137560215C165005293 @default.
• W2137560215 hasConceptScore W2137560215C173608175 @default.
• W2137560215 hasConceptScore W2137560215C2524010 @default.
• W2137560215 hasConceptScore W2137560215C33923547 @default.
• W2137560215 hasConceptScore W2137560215C41008148 @default.
• W2137560215 hasConceptScore W2137560215C45374587 @default.
• W2137560215 hasConceptScore W2137560215C53833338 @default.
• W2137560215 hasConceptScore W2137560215C62520636 @default.
• W2137560215 hasConceptScore W2137560215C76155785 @default.
• W2137560215 hasConceptScore W2137560215C78766204 @default.
• W2137560215 hasConceptScore W2137560215C82876162 @default.
• W2137560215 hasConceptScore W2137560215C93389723 @default.
• W2137560215 hasConceptScore W2137560215C98045186 @default.
• W2137560215 hasConceptScore W2137560215C99844830 @default.
• W2137560215 hasLocation W21375602151 @default.
• W2137560215 hasOpenAccess W2137560215 @default.
• W2137560215 hasPrimaryLocation W21375602151 @default.
• W2137560215 hasRelatedWork W1985608287 @default.
• W2137560215 hasRelatedWork W2022991653 @default.
• W2137560215 hasRelatedWork W2086202544 @default.
• W2137560215 hasRelatedWork W2099930685 @default.

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