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- W2137807823 endingPage "692" @default.
- W2137807823 startingPage "665" @default.
- W2137807823 abstract "Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed." @default.
- W2137807823 created "2016-06-24" @default.
- W2137807823 creator A5053517349 @default.
- W2137807823 date "2001-05-01" @default.
- W2137807823 modified "2023-10-14" @default.
- W2137807823 title "Clock distribution networks in synchronous digital integrated circuits" @default.
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