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- W2138425812 abstract "Abmm- This paper presents two pseudo-random bit sequence (PRBS) generator ICs manufactured in a 200-GHz f, SiGe:C bipolar technology. One circuit uses a seven-stage shift register operating with a half-rate clock followed by a multiplexer nnd provides data rates up to 100 Gb/s. The second circuit contains an eleven-stage shift register and operates with a full-rate clock up to 54 Gb/s. The circuits operate with a supply voltage of -5 V at a power consumption of 1.5 W and 1.9 W, respectively. Both PRBS generator ICs provide a selectable &pattern trigger output. I. INTRODUCTION Pseudo-random bit sequence generators are widely used to provide test signals for circuits such as multiplexers, demultiplexers, flip-flops, and amplifiers. PRBS generators are based on linear feedback shift registers. The number of shifl register stages N determines the length of the resulting pseudorandom sequence, which is ZN-l hits. The large number of flipflops in the shift register, which have to be clocked synchronously, poses the main challenge in the design of highspeed PRBS generators. By making use of special properties of the pseudo-random sequences it is possible to clock the shift register at a fraction (e.g. one half or one quarter) of the output data rate. The output signal is then generated by using additional XOR gates and multiplexers [I]. The fastest PRBS generator ICs reported so far use this multiplexing technique and contain shift registers operating at one half [2, 31 or one quarter [4] of the output data rate. They all have a sequence length of only 127 bits. Monolithic PRBS generators with longer sequences have been presented for data rates of 10 Ghis [5,6]. In this paper we present two PRBS generator ICs. One circuit is designed for high output data rates in the 100 Gb/s range and consists of a seven-stage shift register operating at one half of the output data rate. The second circuit evaluates the possibility of a full-rate design for 40 Gb/s applications, combined with a longer pseudo-random sequence. It contains an eleven-stage shift register operating at the full clock rate. It does not require a multiplexer at its output and is therefore not susceptible to duty-cycle distortion." @default.
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- W2138425812 date "2004-01-01" @default.
- W2138425812 modified "2023-10-03" @default.
- W2138425812 title "100-Gb/s 27-1 and 54-Gb/s 2ll-l PRBS Generators in SiGe Bipolar Technology" @default.
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