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- W2138684606 abstract "We study the nominal delay minimization problem in LUT-based FPGA technology mapping, where interconnect delay is assumed proportional to net fannout size. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K≥3, and remains NP-hard for duplication-free mapping and tree-based mapping for K≥5 (but is polynomial time solvable for K = 2). We also present a simple heuristic to take nominal delay into consideration during LUT mapping for delay minimization." @default.
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- W2138684606 modified "2023-10-12" @default.
- W2138684606 title "On nominal delay minimization in LUT-based FPGA technology mapping" @default.
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- W2138684606 doi "https://doi.org/10.1145/201310.201324" @default.
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