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• W2138865587 abstract "The diminished-one representation has been proposed for RNS-based systems with moduli of the 2 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>n</sup> +1 forms as an encoding that is more efficient than the normal representation in the arithmetic processing units. However, its use necessitates a two-step reverse conversion, in which a diminished-to-normal conversion is first performed before the final residue-to-binary conversion resulting in performance loss. In this paper we introduce efficient modulo 2 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>n</sup> +1 adders, sub tractors and multipliers that accept diminished-one operands at their inputs and derive normal operands at their outputs, that is, we embed the diminished-to-normal conversion within the arithmetic processing. Experimental results show that the proposed one-step approach is more efficient in terms of delay." @default.
• W2138865587 created "2016-06-24" @default.
• W2138865587 creator A5056351845 @default.
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• W2138865587 date "2011-08-01" @default.
• W2138865587 modified "2023-09-26" @default.
• W2138865587 title "Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion" @default.
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• W2138865587 doi "https://doi.org/10.1109/dsd.2011.66" @default.
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