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- W2138991470 abstract "“Many-core” systems based on the Network-on-Chip (NoC) architecture have brought into the fore-front various opportunities and challenges for the deployment of real-time systems. Such real-time systems need timing guarantees to be fulfilled. Therefore, calculating upper-bounds on the end-to-end communication delay between system components is of primaryinterest. In this work, we identify the limitations of an existing approach proposed by [1] and propose different techniques to overcome these limitations. A Tighter Analysis of the Worst-Case End-to-End Communication Delay in Massive Multicores Vincent Nelis, Dakshina Dasari, Borislav Nikolic, Stefan M. Petters CISTER-ISEP Research Centre Polytechnic Institute of Porto, Portugal Email: {nelis, dndi, borni, smp}@isep.ipp.pt Abstract—“Many-core” systems based on the Network-onChip (NoC) architecture have brought into the fore-front various opportunities and challenges for the deployment of real-time systems. Such real-time systems need timing guarantees to be fulfilled. Therefore, calculating upper-bounds on the end-to-end communication delay between system components is of primary interest. In this work, we identify the limitations of an existing approach proposed by [1] and propose different techniques to overcome these limitations.“Many-core” systems based on the Network-onChip (NoC) architecture have brought into the fore-front various opportunities and challenges for the deployment of real-time systems. Such real-time systems need timing guarantees to be fulfilled. Therefore, calculating upper-bounds on the end-to-end communication delay between system components is of primary interest. In this work, we identify the limitations of an existing approach proposed by [1] and propose different techniques to overcome these limitations." @default.
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- W2138991470 date "2011-11-29" @default.
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- W2138991470 title "A Tighter Analysis of the Worst-Case End-to-End Communication Delay in Massive Multicores" @default.
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