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- W2139008889 abstract "Nanoelectromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behaves like an ideal switch. The zero leakage operation has generated lot of interest in low power logic design using these relays [1],[2]. This paper presents various sequential circuit topologies using NEM relays and analyzes their power, performance, and area tradeoffs. The mechanical delay is inversely proportional to the gate-base voltage V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>gb</sub> . This paper also presents an integrated voltage doubler-based flip-flop that improves the performance by 2× by overdriving V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>gb</sub> . An electromechanical model which accounts for the mechanical, electrical, and dispersion effects of the suspended gate relay operating at 1 V with a nominal air gap of 5-10 nm has been developed based on published fabrication results in . Three sequential logic benchmark circuits were designed using NEM relays to verify the correctness of operation of the proposed circuits. This study explores different relay-based latch and flip-flop topologies, proposes fast sequential circuits that can operate at a frequency of 1/2t <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>m</sub> (theoretical fastest frequency for NEM relay logic circuits) and further improves speed of sequential circuits by distributed charge boosting." @default.
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- W2139008889 date "2013-05-01" @default.
- W2139008889 modified "2023-09-26" @default.
- W2139008889 title "NEM Relay-Based Sequential Logic Circuits for Low-Power Design" @default.
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- W2139008889 doi "https://doi.org/10.1109/tnano.2013.2252923" @default.
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