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- W2139146376 abstract "This paper describes a true-single-phase clocking scheme with charge-recycling differential logic (CRDL). The original CRDL circuit is modified for use with only a single-phase clock signal which is never inverted. This circuit achieves low-power and high-speed operation by eliminating the need for slow PMOS-logic blocks in a pipelined configuration, in addition to using charge-recycling technique. XOR/XNOR gates and a pipelined 32-bit adder are constructed with this circuit technique. The simulation results show that the proposed clocking scheme improves power-delay product by 30.1 to 49.8% as compared to the true-single-phase clocking scheme with conventional differential cascode voltage switch (DCVS) logic." @default.
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- W2139146376 date "2002-11-22" @default.
- W2139146376 modified "2023-09-27" @default.
- W2139146376 title "A true single-phase clocking scheme for low-power and high-speed VLSI" @default.
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- W2139146376 doi "https://doi.org/10.1109/iscas.1997.621522" @default.
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