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- W2139954596 abstract "We present an analytic formula for repeater insertion in global interconnects that simultaneously minimizes silicon device area and power dissipation for a given performance /spl tau//sub crit//K where /spl tau//sub crit/ is the minimum possible delay along a global interconnect, with repeaters inserted, and 0<K/spl les/1. Given a certain wire geometry (width and layer assignment) and a factor K, we derive repeater sizes and segment lengths that simultaneously minimize silicon device area and power dissipation associated with the global signal. The analytic model requires only basic device and interconnect characterization data that are easily obtained. The results confirm that performance is expensive in terms of area and power. For example, 85% of performance requires only 30% of the area and 67% of the power compared to the best performance." @default.
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- W2139954596 date "2004-07-20" @default.
- W2139954596 modified "2023-09-23" @default.
- W2139954596 title "Analytic model for area and power constrained optimal repeater insertion" @default.
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- W2139954596 doi "https://doi.org/10.1109/esscirc.2003.1257204" @default.
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