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• W2140020218 abstract "The authors demonstrate the benefit of upgrading simple transistor sizing programs to allow switching individual logic gates among the growing number of design styles available today. The simple transistor sizing algorithm used incorporates gradient search methods along the critical paths at each iteration. Within the basic iteration loop, the authors added heuristics that would switch families of logic gates that met certain conditions. In the case of domino circuits, the switching process is somewhat involved because the logic must usually be changed slightly. The authors found that the addition of even a simple set of switching rules could yield a circuit with significantly improved speed. The design styles considered are standard CMOS, pseudo-nMOS, domino CMOS, and standard BiCMOS. >" @default.
• W2140020218 created "2016-06-24" @default.
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• W2140020218 date "2002-12-09" @default.
• W2140020218 modified "2023-09-27" @default.
• W2140020218 title "CMOS optimization including logic family mixing" @default.
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• W2140020218 doi "https://doi.org/10.1109/iscas.1991.176825" @default.
• W2140020218 hasPublicationYear "2002" @default.
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