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- W2140587552 abstract "This paper presents a high-speed VLSI implementation structure for adder. Innovative serial implementations of carry-look-ahead adders ore developed. The critical path in CLA adders, where the carry is propagated, is implemented using a parallel structure. The supply voltage (V/sub dd/) is 3.9 v which con be lowered to 2.5 v. The adder is in 0.8 /spl mu/m technology. HSPICE simulation shows a total delay of 1.2 ns for 32-bits CLA adder." @default.
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- W2140587552 date "2003-01-20" @default.
- W2140587552 modified "2023-09-24" @default.
- W2140587552 title "Fast carry-look-ahead adder" @default.
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- W2140587552 doi "https://doi.org/10.1109/ccece.1999.807254" @default.
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