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- W2140744425 abstract "On the chip described, dynamic shift registers are combined with high-density serial-parallel-serial charge-coupled-device (SPS CCD) memory blocks in order to obtain a switchable chain of delay blocks with delay values that are powers of two. The shift-register length can be adjusted from 17 to 32767 clock periods. The tradeoff between the delay implementations is presented. A detailed description of the SPS CCD are given. The chip has been realized in a 2.5-/spl mu/m NMOS process with CCD option." @default.
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- W2140744425 date "1987-06-01" @default.
- W2140744425 modified "2023-09-27" @default.
- W2140744425 title "A 32-Kbit variable-length shift register for digital audio application" @default.
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- W2140744425 doi "https://doi.org/10.1109/jssc.1987.1052741" @default.
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