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- W2141330236 abstract "Previous code compression research on embedded systems was based on typical RISC instruction code. THUMB from ARM Ltd is a compacted 16-bits instruction set showing a great code density than its original 32-bits ARM instruction. Our research shows that THUMB code is compressible and a further 10-15% code size reduction on THUMB code can be expected using our proposed new architecture - code compressed THUMB processor. In our proposal, level 2 cache or additional RAM space is introduced to serve as the temporary storage for decompressed program blocks. A software implementation of the architecture is proposed and we have implemented a software prototype based on ARM922T processor, which runs on the ARMulator" @default.
- W2141330236 created "2016-06-24" @default.
- W2141330236 creator A5031939356 @default.
- W2141330236 creator A5056464716 @default.
- W2141330236 date "2004-07-08" @default.
- W2141330236 modified "2023-10-05" @default.
- W2141330236 title "Code compression for the embedded ARM/THUMB processor" @default.
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- W2141330236 doi "https://doi.org/10.1109/idaacs.2003.1249510" @default.
- W2141330236 hasPublicationYear "2004" @default.
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