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• W2141592621 abstract "Reconfigurable processor architectures (RAs) have been proving as an effective way to couple significant performance improvements with severe energy constraints, such as those imposed by modern portable real-time applications. XiRisc is a VLIW RISC processor architecture featuring a reconfigurable dataflow-oriented functional unit, the so-called PiCoGA, allowing run-time dynamic extension of the instruction set. In this paper, we propose a LISA-based instruction set simulator (ISS) for the reconfigurable processor, retargetable through a dynamically linked library that emulates instruction set extension. The ISS comprises a SystemC system-level model with embedded bus architecture and memory hierarchy (on-chip and off-chip) to provide a reconfigurable system-on-chip performance evaluator." @default.
• W2141592621 created "2016-06-24" @default.
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• W2141592621 date "2005-04-19" @default.
• W2141592621 modified "2023-10-17" @default.
• W2141592621 title "A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture" @default.
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• W2141592621 doi "https://doi.org/10.1109/ipdps.2005.14" @default.
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