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• W2142155217 abstract "Abstract This paper reviews the normally‐off (N ‐ off) and normally‐on (N ‐ on) SiC junction field effect transistor (JFET) concepts and presents an innovative all‐epitaxial double‐gate trench JFET (DGTJFET) structure. The DGTJFET design combines the advantages of lateral and buried gate JFET concepts. The lateral JFET advantage is the epitaxial definition of the channel width and the buried gate JFET advantage is the small cell size. In the DGTJFET process the epitaxial embedded growth in trenches facilitates the small cell pitch and the vertical direction of the channel. A detailed numerical simulation analysis compares the potential of the DGTJFET design with reported lateral channel and buried gate JFET structures. Migration enhanced embedded epitaxy (ME 3 ) and planarization processes were developed to realize narrow cell pitch DGTJFETs for high‐density power integration. The highly doped vertical channel of the DGTJFET defined by the ME 3 growth process makes it possible to accurately control the sub‐micron channel dimensions in order to realize a low specific on‐state resistance ( R ON ) and a high saturation current capability. The anisotropic nature of SiC is taken into account for the channel design considerations. The successful application of the new process technologies for the development of the all‐epitaxial DGTJFETs is discussed. Fabricated 5.5 μm cell pitch 4H‐SiC DGTJFETs demonstrate the saturation current density capability of more than 1000 A/cm 2 . N ‐ off and N ‐ on DGTJFETs with 2.25 mm squared chip size and 9.5 μm cell pitch output 15 A and 20 A at gate voltage of 2.5 V and drain voltage of 5.0 V. The specific R ON of the N ‐ off and N ‐ on DGTJFETs is at room temperature 8.1 m Ω cm 2 and 6.3 mΩ cm 2 , respectively, indicating that N ‐ off devices can be realized at the expense of a slight increase in specific R ON of approximately 25%. DGTJFETs with a 13 μm drift layer doped to 5.0 × 10 15 cm –3 are demonstrated with a breakdown voltage in the range of 1200 V to 1550 V at the wafer level with a leakage current below 10 μA. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)" @default.
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• W2142155217 date "2009-10-01" @default.
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• W2142155217 title "Design, process, and performance of all-epitaxial normally-off SiC JFETs" @default.
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• W2142155217 doi "https://doi.org/10.1002/pssa.200925254" @default.
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