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• W2142364191 abstract "The use of the Cooley-Tukey algorithm for computing the 1-d FFT lends itself to a particular matrix factorization which suggests direct implementation by linearly-connected systolic arrays. Here we present a new systolic architecture that embodies this algorithm. This implementation requires a smaller number of processors and a smaller number of memory cells than other recent implementations, as well as having all the advantages of systolic arrays. For the implementation of the decimation-in-frequency case, word-serial data input allows continuous real-time operation without the need of a serial-to-parallel conversion device. No control or data stream switching is necessary. Computer simulation of this architecture was done in the context of a 1024 point DFT with a fixed point processor, and CMOS processor implementation has started.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
• W2142364191 created "2016-06-24" @default.
• W2142364191 creator A5071846444 @default.
• W2142364191 date "1994-04-01" @default.
• W2142364191 modified "2023-09-27" @default.
• W2142364191 title "FFT computation with systolic arrays, a new architecture" @default.
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• W2142364191 doi "https://doi.org/10.1109/82.285710" @default.
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