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• W2142562131 abstract "A low-jitter clock is important to large scale sensors. A new method using low cost DAC, VCXO and FPGA counter to generate distributed synchronous clocks, which is called digital synchronous clock (DDSC), can decrease 60% jitter comparing with traditional PLL (from 36.510ps down to 14.608ps). When these two clocks are used as the source of a 24bit ADC system, the result shows that DDSC makes the total harmonic distortion (THD) increase dramatically (from 106dB to 117dB)." @default.
• W2142562131 created "2016-06-24" @default.
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• W2142562131 date "2009-05-01" @default.
• W2142562131 modified "2023-09-22" @default.
• W2142562131 title "A low-jitter distributed synchronous clock using DAC" @default.
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• W2142562131 doi "https://doi.org/10.1109/rtc.2009.5321665" @default.
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