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• W2143649204 abstract "This paper presents a deterministic test pattern generator for combinational circuits, called CONTEST, which can efficiently handle various gate level fault models: stuck-at faults, function conversions, bridging faults, transition faults and faults with additional fault detection conditions. CONTEST is part of a complete test generation system for non-classical faults which consists of a test pattern generator, a fault simulator and a fault list generator. The fault list generator uses a library-based fault modeling strategy which allows the specification of realistic target fault sets. Experimental results show that CONTEST can efficiently handle non-classical faults on the gate level. For a complex target fault set which encompasses for example stuck-at, stuck-open and bridging faults, a test efficiency of 100% has been achieved for each of the ISCAS benchmark circuits containing up to 38,000 nodes." @default.
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• W2143649204 date "2002-11-19" @default.
• W2143649204 modified "2023-09-27" @default.
• W2143649204 title "Deterministic test generation for non-classical faults on the gate level" @default.
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• W2143649204 doi "https://doi.org/10.1109/ats.1995.485343" @default.
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