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• W2143788345 abstract "An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance." @default.
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• W2143788345 date "1999-06-01" @default.
• W2143788345 modified "2023-10-05" @default.
• W2143788345 title "MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)" @default.
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• W2143788345 doi "https://doi.org/10.1109/55.767102" @default.
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