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- W2143946297 abstract "As the chip density grows, wiring circuits on a VLSI chip becomes hard. It is then important to leave feed-through channels in the layouts of cells and macros. One strategy to achieve this goal is to keep wires on their respective wiring grids. This requirement presents a new constraint to the compaction problem of cells and macros. A new efficient algorithm is proposed to solve such a compaction problem on multiple grids. The worst-case time complexity of the algorithm is O((M+1) ( mod V mod + mod E mod )). The algorithm has been implemented in a compactor and applied to the layout designs for both microprocessor chips and ASIC chips. >" @default.
- W2143946297 created "2016-06-24" @default.
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- W2143946297 date "2002-12-10" @default.
- W2143946297 modified "2023-09-26" @default.
- W2143946297 title "A layout compaction algorithm with multiple grid constraints" @default.
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- W2143946297 doi "https://doi.org/10.1109/iccd.1991.139837" @default.
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