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- W2144132011 abstract "In this brief, we present an efficient design of a shared architecture to compute two 8-point Daubechies wavelet transforms. The architecture is based on a two-level folded mapping technique that is developed on the factorization and decomposition of transform matrices exploiting the symmetrical structure. The chip occupies a 2.08-mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> silicon area, runs at 100 MHz, and consumes 4.51 mW of power in 0.18-m CMOS technology." @default.
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- W2144132011 date "2010-09-01" @default.
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- W2144132011 title "Area- and Power-Efficient Design of Daubechies Wavelet Transforms Using Folded AIQ Mapping" @default.
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- W2144132011 doi "https://doi.org/10.1109/tcsii.2010.2056111" @default.
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