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- W2144915188 abstract "Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be power-gated. In this paper, we first develop an accurate FPGA power model and then design novel Vdd-programmable interconnect switches with minimum number of configuration SRAM cells. Applying our power model to placed and routed benchmark circuits, we evaluate Vdd-programmable FPGA architecture using the new switches. The best architecture in our study uses Vdd-programmable logic blocks and Vdd-gateable interconnects. Compared to the baseline architecture similar to the leading commercial architecture, the best architecture reduces the minimal energy-delay product by 44.14% with 48% area overhead and 3% SRAM cell increase. Our evaluation results also show that LUT size 4 always gives the lowest energy consumption while LUT size 7 always leads to the highest performance for all evaluated architectures." @default.
- W2144915188 created "2016-06-24" @default.
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- W2144915188 date "2005-02-20" @default.
- W2144915188 modified "2023-10-18" @default.
- W2144915188 title "Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability" @default.
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- W2144915188 doi "https://doi.org/10.1145/1046192.1046218" @default.
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