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• W2145383942 abstract "A simple embedded DRAM (eDRAM) process that minimizes the front-end add-on cost is presented for 0.16-/spl mu/m CMOS technologies. The structure results in a low-leakage device (<20 fA/cell at 100/spl deg/C) suitable for future generations of eDRAMs. Without using poly-Si plugs or metal-0 bit-line runners, topography is identical to the core LOGIC process. Low-temperature MIM capacitors are easily integrated using the W-plugs of metal-2 level. The number of total additional lithographic steps is only 3-5." @default.
• W2145383942 created "2016-06-24" @default.
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• W2145383942 date "2002-11-07" @default.
• W2145383942 modified "2023-09-25" @default.
• W2145383942 title "A simple embedded DRAM process for 0.16-μm CMOS technologies" @default.
• W2145383942 cites W2037560907 @default.
• W2145383942 doi "https://doi.org/10.1109/vlsit.2000.852769" @default.
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