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- W2145440724 abstract "Abstract In this paper, one step ferroelectric capacitor etching technology has been developed. Stacked capacitor layers with 0.75μm height were etched with a TiN hard mask. Etch selectivity increases as oxygen ratio in capacitor etching gases increases. After etching the electrodes and the PZT film, the slope of the stack capacitor was around 72 degrees and it has been proven that no si dew all fence was generated during the capacitor etching process and its leakage current was below 10–6A/cm2. The 0.9×0.9μm2 area capacitor for a 16M FRAM density has been well fabricated by one step etching process with very high selectivity to the mask." @default.
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- W2145440724 date "2001-01-01" @default.
- W2145440724 modified "2023-09-24" @default.
- W2145440724 title "Stacked FRAM capacitor etching process for high density application" @default.
- W2145440724 cites W2133939764 @default.
- W2145440724 doi "https://doi.org/10.1080/10584580108015670" @default.
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