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- W2145710086 abstract "A 113 GHz 176.4 mW transmitter and receiver chipset using 65 nm CMOS technology is presented. To achieve low power consumption, an amplitude shift keying modulation with a simple circuit is adopted for this chipset, and the transmitter does not have a power amplifier. The power consumptions of the transmitter and receiver are 65.5 and 110.9 mW, respectively. A 2.5 Gbps pseudorandom bit sequence is successfully transferred from the transmitter to the receiver by wireless propagation through a distance of 0.2 m with a bit error rate of less than 10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>-8</sup> . The transmitter has an output power of -0.05 dBm." @default.
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- W2145710086 date "2012-12-01" @default.
- W2145710086 modified "2023-09-23" @default.
- W2145710086 title "A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology" @default.
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- W2145710086 doi "https://doi.org/10.1109/apmc.2012.6421624" @default.
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