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- W2145801698 abstract "Pass transistor logic and complementary pass-transistor logic (CPL) are becoming increasingly important in the design of a specific class of digital integrated circuits owing to their speed and power efficiency as compared with conventional CMOS logic. In this paper, a simple and very accurate technique for the timing analysis of gates that involve pass transistor logic is presented. This investigation offers for the first time the possibility of simulating pass transistor and CPL gates by partitioning the behaviour of complex structures into well defined subcircuits whose interaction is studied separately. Using the proposed analysis, which is validated by results for two submicron technologies, most pass-transistor logic styles can be modelled efficiently. Consequently, a significant speed advantage can be gained compared with simulation tools that employ numerical methods such as SPICE." @default.
- W2145801698 created "2016-06-24" @default.
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- W2145801698 date "2001-09-01" @default.
- W2145801698 modified "2023-09-25" @default.
- W2145801698 title "Modelling the operation of pass transistor and CPL gates" @default.
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- W2145801698 doi "https://doi.org/10.1080/00207210110066185" @default.
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