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- W2146006985 abstract "In multimedia Systems-on-Chips, the design of specialized IEEE-754-compliant floating point arithmetic units (FPU) is critical with respect to both operating speed and silicon area demand. Leading one anticipation is a well-known issue in the implementation of high speed FPUs. We investigated a novel leading one anticipation algorithm allowing us to significantly reduce the anticipation failure rate with respect to the state-of the art. We embedded our technique into a complete FPU and compared its performance against existing solutions, definitely showing both area savings and total latency reduction." @default.
- W2146006985 created "2016-06-24" @default.
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- W2146006985 date "2012-03-01" @default.
- W2146006985 modified "2023-09-27" @default.
- W2146006985 title "A Novel FPGA based Leading One Anticipation Algorithm for Floating Point Arithmetic Units" @default.
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- W2146006985 doi "https://doi.org/10.11591/ijres.v1.i1.pp19-24" @default.
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