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- W2146102610 abstract "A previous realization of a fault tolerant architecture at CMOS level, while guaranteeing the correct behavior of the circuit both in the fault-free situation and in the presence of stuck-on faults, was characterized by a neither null nor +V/sub dd/ output voltage when faults occurred. An improved architecture is here presented, which by adding additional transistors, achieves the fault tolerance property without degrading the performance of the circuit in terms of output voltage and short circuit current." @default.
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- W2146102610 date "2002-11-22" @default.
- W2146102610 modified "2023-09-26" @default.
- W2146102610 title "An improved fault tolerant architecture at CMOS level" @default.
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- W2146102610 doi "https://doi.org/10.1109/iscas.1997.612891" @default.
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