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• W2146234502 abstract "The astonishing success story of microelectronics cannot go on indefinitely. In fact, oncedevices reach the few-atom scale (nanoelectronics), transient quantum effects are expectedto impair their behaviour. Fault tolerant techniques will then be required. The aim of thisthesis is to investigate the problem of transient errors in nanoelectronic devices. Transienterror rates for a selection of nanoelectronic gates, based upon quantum cellular automataand single electron devices, in which the electrostatic interaction between electrons is usedto create Boolean circuits, are estimated. On the bases of such results, various fault tolerantsolutions are proposed, for both logic and memory nanochips. As for logic chips, traditionaltechniques are found to be unsuitable. A new technique, in which the voting approach oftriple modular redundancy (TMR) is extended by cascading TMR units composed ofnanogate clusters, is proposed and generalised to other voting approaches. For memorychips, an error correcting code approach is found to be suitable. Various codes areconsidered and a lookup table approach is proposed for encoding and decoding. We arethen able to give estimations for the redundancy level to be provided on nanochips, so as tomake their mean time between failures acceptable. It is found that, for logic chips, spaceredundancies up to a few tens are required, if mean times between failures have to be of theorder of a few years. Space redundancy can also be traded for time redundancy. As formemory chips, mean times between failures of the order of a few years are found to implyboth space and time redundancies of the order of ten." @default.
• W2146234502 created "2016-06-24" @default.
• W2146234502 creator A5028878640 @default.
• W2146234502 date "2008-11-01" @default.
• W2146234502 modified "2023-09-26" @default.
• W2146234502 title "Fault tolerance issues in nanoelectronics" @default.
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• W2146234502 hasPublicationYear "2008" @default.
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