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- W2146378652 abstract "We present a system level architecture for a scalable, mixed-signal, asynchronous processor, aimed at cortical computations. The design has been implemented in MIT Lincoln Lab's three-tier SOI-CMOS 0.18/spl mu/m digital process. The main circuits are distributed in the two tiers; an asynchronous address-event based read/write middle tier and an odd symmetric spatial filter (8 orientations) on the bottom tier. The top tier includes a photosensitive pixel array (64/spl times/64) to facilitate testing and characterization of the system. A highspeed 2-phase asynchronous chip-to-chip communication protocol is built-in to facilitate system scalability." @default.
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- W2146378652 date "2006-09-22" @default.
- W2146378652 modified "2023-09-25" @default.
- W2146378652 title "A mixed analog/digital asynchronous processor for cortical computations in 3D SOI-CMOS" @default.
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- W2146378652 doi "https://doi.org/10.1109/iscas.2006.1693743" @default.
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