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• W2146606114 abstract "An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power." @default.
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• W2146606114 date "2013-06-12" @default.
• W2146606114 modified "2023-09-26" @default.
• W2146606114 title "A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO" @default.
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