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- W2146760946 abstract "In this paper, a 40 V versatile HV LDMOS technology with lower R <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>dson</sub> has been developed in the existing 0.18 mum LV CMOS process. The HV LDMOS are designed by using DOE concept on the simulation results from T-supreme followed by Medici. The process complexity to incorporate the HV kept as simple as possible which does not affect much due to baseline. DOE model are constructed from both the critical layout dimensions and implantation scheme. The optimized condition from DOE model provides good breakdown voltage with low R <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>dson</sub> , the values are BVDSS ~77 V & ~59 V; R <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>dson</sub> mu 84 mOmegamm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> & mu192 mOmegamm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> for n-LDMOS p-LDMOS respectively. Final tuning of the process & layout done by splits to improve the other device parameters such as leakage current, substrate current for better reliability & etc." @default.
- W2146760946 created "2016-06-24" @default.
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- W2146760946 date "2008-11-01" @default.
- W2146760946 modified "2023-09-26" @default.
- W2146760946 title "Design and Optimization of 40V, 0.18μm versatile HVL-DMOS device with DOE" @default.
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- W2146760946 doi "https://doi.org/10.1109/smelec.2008.4770265" @default.
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