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• W2147446937 abstract "On-chip interconnection networks for future systems on chip (SoC) will have to deal with the increasing sensitivity of global wires to noise sources such as crosstalk or power supply noise. Hence, transient delay and logic faults are likely to reduce the reliability of across-chip communication. Given the reduced power budgets for SoCs, in this paper, we develop solutions for combined energy minimization and communication reliability control. Redundant bus coding is proved to be an effective technique for trading off energy against reliability, so that the most efficient scheme can be selected to meet predefined reliability requirements in a low signal-to-noise ratio regime. We model on-chip interconnects as noisy channels and evaluate the impact of two error recovery schemes on energy efficiency: correction at the receiver stage versus retransmission of corrupted data. The analysis is performed in a realistic SoC setting, and holds both for shared communication resources and for peer-to-peer links in a network of interconnects. We provide SoC designers with guidelines for the selection of energy efficient error-control schemes for communication architectures." @default.
• W2147446937 created "2016-06-24" @default.
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• W2147446937 date "2005-06-01" @default.
• W2147446937 modified "2023-10-01" @default.
• W2147446937 title "Error control schemes for on-chip communication links: the energy-reliability tradeoff" @default.
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• W2147446937 doi "https://doi.org/10.1109/tcad.2005.847907" @default.
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