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• W2147862927 abstract "AbstractAlthough adaptive strategies based on the Measure-and-Control (M&C) design paradigm have been proven to be effective methods to achieve aging resilient circuits, their implementation requires accurate monitoring architectures and integrated aging sensors. This paper presents a new on-chip, fully digital monitoring architecture for tracking BTI-induced aging effects on digital ICs. The proposed solution is based on delay-to-threshold coherency of MOS devices and measures differential delay across pass-transistor chains. The aging monitor is conceived and designed as a self-contained standard gate consisting of reference and under stress sensors with embedded measurement circuitries and a control structure for data capturing. To guarantee independent measurements of both Positive- and Negative-BTI, two separate aging sensor blocks are used. Detailed SPICE simulations conducted for a low-power 40nm CMOS technology indicates the actual capability of the proposed circuit to capture BTI-induced aging.KeywordsNBTIPBTIreliability sensorsensor system designAging MeasurementDesign for Reliability" @default.
• W2147862927 created "2016-06-24" @default.
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• W2147862927 date "2013-01-01" @default.
• W2147862927 modified "2023-09-27" @default.
• W2147862927 title "On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture" @default.
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• W2147862927 doi "https://doi.org/10.1007/978-3-642-36157-9_16" @default.
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