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• W2148049933 abstract "A new systolic array without matrix transposition hardware is proposed to compute the two-dimensional discrete cosine transform (2-D DCT) based on the row-column decomposition. This architecture uses N/sup 2/ multipliers to evaluate N/spl times/N-point DCTs at a rate of one complete transform per N clock cycles, where N is even. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to existing pipelined regular architectures for the 2-D DCT, the proposed one has better throughput performance, smaller area-time complexity, and lower communication complexity. The new idea for the 2-D DCT is also extended to derive a similar systolic array for the 2-D inverse discrete cosine transform (IDCT). Simulation results demonstrate that the proposed 2-D DCT and IDCT architectures have good fixed-point error performance for both real image and random data. As a consequence, they are useful for applications where very high throughput rates are required.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
• W2148049933 created "2016-06-24" @default.
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• W2148049933 date "1995-04-01" @default.
• W2148049933 modified "2023-09-24" @default.
• W2148049933 title "New systolic array implementation of the 2-D discrete cosine transform and its inverse" @default.
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• W2148049933 doi "https://doi.org/10.1109/76.388063" @default.
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