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• W2148442264 abstract "In this paper, the materials and processing challenges for the fabrication of high-quality, ultra-thin (EOT<1 nm) dual-poly high-k gate stack for sub-100 nm CMOS technology are reviewed along with recent results on CVD HfO/sub 2/. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve the thinnest possible EOT (equivalent oxide thickness) is discussed. Results are presented on the thermal stability of high-k materials, and interfacial reactions of high-k/Si and high-k/gate electrode interfaces. We also discuss key factors that govern the conduction and degradation mechanisms in high-k gate stacks. Finally, recent work on metal nitrides as possible gate electrode materials is reviewed and the upper thermal budget limit for such materials is discussed." @default.
• W2148442264 created "2016-06-24" @default.
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• W2148442264 date "2002-11-13" @default.
• W2148442264 modified "2023-10-01" @default.
• W2148442264 title "Dual-poly CVD HfO/sub 2/ gate stack for sub-100 nm CMOS technology" @default.
• W2148442264 cites W2101781928 @default.
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• W2148442264 doi "https://doi.org/10.1109/iwgi.2001.967552" @default.
• W2148442264 hasPublicationYear "2002" @default.
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