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• W2148760151 abstract "In this letter, we demonstrate an channel n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with silicon interface passivation layer (IPL) and gate oxide. The effects of the source/drain activation temperature, postdeposition annealing temperature, and thickness of silicon IPL on the transistor characteristics have been investigated. The results suggest that the annealing temperatures are critical for determining the transistor performances. Even though is easier to obtain the unpinned surface Fermi level compared to GaAs, applying silicon IPL still improves the nMOSFET characteristics significantly through engineering the interface quality." @default.
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• W2148760151 date "2009-01-01" @default.
• W2148760151 modified "2023-10-03" @default.
• W2148760151 title "Effects of Anneal and Silicon Interface Passivation Layer Thickness on Device Characteristics of In[sub 0.53]Ga[sub 0.47]As Metal-Oxide-Semiconductor Field-Effect Transistors" @default.
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• W2148760151 doi "https://doi.org/10.1149/1.3074298" @default.
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