Matches in SemOpenAlex for { <https://semopenalex.org/work/W2148889403> ?p ?o ?g. }
Showing items 1 to 81 of
81
with 100 items per page.
- W2148889403 abstract "With burgeoning growth of mobile systems, multiprocessor System-on-Chip (MPSoC) connected via Network-on-Chip (NoC) has become ubiquitous. A typical MPSoC in mobile applications consists of multiple CPU cores of varying capabilities, GPU cores, DSP cores, and crypto accelerators and such cores differ widely in their physical size and their bandwidth requirements. Traditional mesh based NoC systems work well for regular structures, but do not map well to heterogeneous MPSoCs. In MPSoC programming model, an application consists of tasks, that represent a unit of work on a core which can be executed asynchronously. The communication between tasks is represented in the form of a directed acyclic graph. The temporal burstness of data which arise from programming model provide opportunity for multiplexing communication between cores, which may be advantageous in reducing network size. Often a task graph needs to meet a real-time deadline. The actual execution time may vary based on the application data. The uncertainty in the execution time may be modeled by a statistical distribution, which further complicates the NoC design. In this paper, we present a synthesis method for hierarchical design of NoC for a given task graph system deadline, that optimizes for router area. A 2-phase design flow is proposed, which consists of topology generation and statistical analysis in an iterative loop. We adopt proportion of Monte-Carlo test cases that meet the deadline as a metric for goodness. The proposed solution is compared against static design approach and simulated annealing (SA) based network generation. On an average, a performance benefit of 10% over SA, 16% over standard mesh and 30% over static design was obtained and a total router area benefit of 59% over SA, 48% over mesh and 55% over static design was observed" @default.
- W2148889403 created "2016-06-24" @default.
- W2148889403 creator A5054064879 @default.
- W2148889403 creator A5073516448 @default.
- W2148889403 date "2014-07-01" @default.
- W2148889403 modified "2023-09-25" @default.
- W2148889403 title "Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip" @default.
- W2148889403 cites W1974843053 @default.
- W2148889403 cites W2039968196 @default.
- W2148889403 cites W2077505860 @default.
- W2148889403 cites W2089266617 @default.
- W2148889403 cites W2095965878 @default.
- W2148889403 cites W2106665917 @default.
- W2148889403 cites W2119865827 @default.
- W2148889403 cites W2120538858 @default.
- W2148889403 cites W2121182670 @default.
- W2148889403 cites W2123456523 @default.
- W2148889403 cites W2129442721 @default.
- W2148889403 cites W2132249049 @default.
- W2148889403 cites W2159247054 @default.
- W2148889403 cites W2161455936 @default.
- W2148889403 cites W2170954333 @default.
- W2148889403 doi "https://doi.org/10.1109/isvlsi.2014.96" @default.
- W2148889403 hasPublicationYear "2014" @default.
- W2148889403 type Work @default.
- W2148889403 sameAs 2148889403 @default.
- W2148889403 citedByCount "3" @default.
- W2148889403 countsByYear W21488894032015 @default.
- W2148889403 countsByYear W21488894032019 @default.
- W2148889403 crossrefType "proceedings-article" @default.
- W2148889403 hasAuthorship W2148889403A5054064879 @default.
- W2148889403 hasAuthorship W2148889403A5073516448 @default.
- W2148889403 hasConcept C118021083 @default.
- W2148889403 hasConcept C120314980 @default.
- W2148889403 hasConcept C128519102 @default.
- W2148889403 hasConcept C149635348 @default.
- W2148889403 hasConcept C173608175 @default.
- W2148889403 hasConcept C2775896111 @default.
- W2148889403 hasConcept C2777187653 @default.
- W2148889403 hasConcept C31258907 @default.
- W2148889403 hasConcept C41008148 @default.
- W2148889403 hasConcept C4822641 @default.
- W2148889403 hasConcept C78766204 @default.
- W2148889403 hasConceptScore W2148889403C118021083 @default.
- W2148889403 hasConceptScore W2148889403C120314980 @default.
- W2148889403 hasConceptScore W2148889403C128519102 @default.
- W2148889403 hasConceptScore W2148889403C149635348 @default.
- W2148889403 hasConceptScore W2148889403C173608175 @default.
- W2148889403 hasConceptScore W2148889403C2775896111 @default.
- W2148889403 hasConceptScore W2148889403C2777187653 @default.
- W2148889403 hasConceptScore W2148889403C31258907 @default.
- W2148889403 hasConceptScore W2148889403C41008148 @default.
- W2148889403 hasConceptScore W2148889403C4822641 @default.
- W2148889403 hasConceptScore W2148889403C78766204 @default.
- W2148889403 hasLocation W21488894031 @default.
- W2148889403 hasOpenAccess W2148889403 @default.
- W2148889403 hasPrimaryLocation W21488894031 @default.
- W2148889403 hasRelatedWork W1972741450 @default.
- W2148889403 hasRelatedWork W1975908267 @default.
- W2148889403 hasRelatedWork W1997754872 @default.
- W2148889403 hasRelatedWork W2032995057 @default.
- W2148889403 hasRelatedWork W2036551376 @default.
- W2148889403 hasRelatedWork W2068384573 @default.
- W2148889403 hasRelatedWork W2072705935 @default.
- W2148889403 hasRelatedWork W2073617174 @default.
- W2148889403 hasRelatedWork W2080018716 @default.
- W2148889403 hasRelatedWork W2097071547 @default.
- W2148889403 hasRelatedWork W2162064567 @default.
- W2148889403 hasRelatedWork W2318454936 @default.
- W2148889403 hasRelatedWork W2356024207 @default.
- W2148889403 hasRelatedWork W2371369302 @default.
- W2148889403 hasRelatedWork W2546389195 @default.
- W2148889403 hasRelatedWork W2772660694 @default.
- W2148889403 hasRelatedWork W2792139368 @default.
- W2148889403 hasRelatedWork W3137626123 @default.
- W2148889403 hasRelatedWork W626972714 @default.
- W2148889403 hasRelatedWork W959172305 @default.
- W2148889403 isParatext "false" @default.
- W2148889403 isRetracted "false" @default.
- W2148889403 magId "2148889403" @default.
- W2148889403 workType "article" @default.