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• W2148919406 abstract "This paper proposes a reconfigurable pipelined multiplier architecture that achieves high performance and very low energy dissipation by adapting its structure to computational requirements over time. In this reconfigurable multiplier energy is saved by disabling and bypassing an appropriate number of pipeline stages whenever input data rates are low. To evaluate the efficiency of our multiplier architecture, we have designed a multiplier-based inverse quantizer (IQ) for MPEG-2 MP@ML. Pipelines are dynamically reconfigured according to the size of the picture and the number of nonzero quantized DCT coefficients per block. In comparison with corresponding multiplier implementations that use conventional pipelines, our reconfigurable multipliers dissipate about 31-58% less energy. Relative energy savings increase with decreasing data rates, since our reconfigurable structures stay in a low energy configuration for proportionately longer time." @default.
• W2148919406 created "2016-06-24" @default.
• W2148919406 creator A5041839124 @default.
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• W2148919406 date "2002-11-07" @default.
• W2148919406 modified "2023-09-28" @default.
• W2148919406 title "Reconfigurable low energy multiplier for multimedia system design" @default.
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• W2148919406 doi "https://doi.org/10.1109/iwv.2000.844541" @default.
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