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• W2148946314 abstract "This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-/spl mu/m heterojunction FETs (HJFETs) which have about half the external gate fringing capacitance (C/sub f//sup ext/) of conventional T-shaped gate HJFET's. By introducing a T-shaped SiO/sub 2/-opening technique based on two-step dry-etching with W-film masks, we fabricated 0.1-/spl mu/m gate-openings which were suitable for reducing the C/sub f//sup ext/ and filling gate-metals with voidless. The fine gate-openings are completely filled with refractory WSi/Ti/Pt/Au gate-metal by using WSi-collimated sputtering and electroless Au-plating, resulting in high performance 0.1-/spl mu/m DDS gate HJFETs are fabricated. The 0.1-/spl mu/m n-Al/sub 0.2/Ga/sub 0.8/As/i-In/sub 0.15/Ga/sub 0.85/As pseudomorphic DDS gate HJFETs exhibited an excellent V/sub th/ standard-deviation (/spl sigma/V/sub th/) of 39 mV because dry-etching techniques were used in all etching-processes. Also, an HJFET covered with SiO/sub 2/ passivation film had very high performance with an f/sub T/ of 120 GHz and an f/sub max/ of 165 GHz, due to the low C/sub f//sup ext/ with the DDS gate structure. In addition, a high f/sub T/ of 151 GHz and an f/sub max/ of 186 GHz were obtained without a SiO/sub 2/ passivation film. This fabrication technology shows great promise for high-speed IC applications." @default.
• W2148946314 created "2016-06-24" @default.
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• W2148946314 date "1999-05-01" @default.
• W2148946314 modified "2023-09-24" @default.
• W2148946314 title "An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET with reduced gate-fringing-capacitance" @default.
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• W2148946314 doi "https://doi.org/10.1109/16.760390" @default.
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