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• W2149058414 abstract "Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is, however, still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability blocks is proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs (programmable logic devices), using a simple and powerful HDL (hardware design language). >" @default.
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• W2149058414 date "2002-12-30" @default.
• W2149058414 modified "2023-09-27" @default.
• W2149058414 title "An HDL approach to board-level BIST" @default.
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• W2149058414 doi "https://doi.org/10.1109/eurdac.1993.410669" @default.
• W2149058414 hasPublicationYear "2002" @default.
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